In a typical first-in-first-out ("FIFO") memory, a write index and a read index are used to determine whether the FIFO is empty or full. The write and read indices may be maintained by a counter. If a synchronous binary counter is used to maintain the write and read indices, then two or more digital logic bits of the synchronous binary counter may simultaneously change at a particular time in response to a clock signal, resulting in undesirable transition noise and complex timing conditions. If a single transition counter is used to maintain the write and read indices, then only one digital logic bit of the counter changes in response to a particular clock signal.
Nevertheless, a traditional single transition counter is significantly larger and slower than a typical synchronous binary counter, because a traditional single transition counter requires additional circuitry for extensive combination logic to implement the single transition counting approach, particularly when large bit counts are to be achieved. Moreover, the additional combination logic circuitry requires increased power. Also, since traditional single transition counters require extensive combination logic, they cannot be modularized and repeatedly duplicated as bits are added to the counter to achieve a predetermined maximum count. Modularization is particularly important for application specific integrated circuit ("ASIC") compiler programs that produce an integrated circuit design based upon parameters specified for a particular integrated circuit application. By repeatedly duplicating identical modules, integrated circuit designs produced by ASIC compiler programs become more simplified, easier to troubleshoot, and easier to analyze in terms of operating characteristics. The extensive combination logic of traditional single transition counters further restricts the maximum counting speed of such counters due to signal delays through the combination logic gates. For up/down counting, a traditional up/down counter requires a first set of combination logic for incrementing the count value, along with a second set of combination logic for decrementing the count value. In addition to the required combination logic, a traditional up-down counter further requires a multiplexer to selectively output either the incremented or decremented count value, thereby requiring even more circuitry, which is undesirable.
Consequently, a need has arisen for a method and circuitry for modularized single transition counting, which substantially overcomes shortcomings of synchronous binary counters, of traditional single transition counters, and of traditional up-down counters.